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Western Digital Brings Memory Closer to Compute With New RISC-V Innovations and Strategic Partnerships
December 10, 2019 By BlueAlly
Company Deepens Commitment to RISC-V with Open Sourcing of the First Dual-Threaded, Embedded Processor Core and Expanded Support for SweRV Core Commercialization
RISC-V Summit 2019, San Jose, CA - Dec 10, 2019
Western Digital Corp. (NASDAQ: WDC) today unveiled new innovations and ecosystem partnerships intended to foster collaborative innovation, and the development and commercialization of purpose-built technologies based on RISC-V. New additions to the company's open sourced RISC-V-based SweRV Core™ family include the world's first dual-threaded, commercial, embedded RISC-V core, SweRV Core EH2, and the company's smallest SweRV Core to date, EL2. In addition, the company is announcing a hardware reference design for OmniXtend™, the open "direct to cache over Ethernet" fabric protocol developed by Western Digital.
Further details on Western Digital's new RISC-V innovations, as well as the company's expanded collaboration with CHIPS ALLIANCE and Codasip, can be found below.
QUOTE:
"Moving into 2020, we face the enormous challenge of continuing to efficiently support data's exponentially growing scale and velocity, as well as an equally significant opportunity to discover new value from it. Open, collaborative innovation that brings data closer to processing power is essential to addressing both," said Martin Fink, former CTO and strategic advisor to the CEO at Western Digital. "Our newest open-source additions to the SweRV Core portfolio and expanded work with the ecosystem further our commitment to accelerating the RISC-V initiative and demonstrate our progress towards shaping the future of purpose-built data infrastructure."
NEWS HIGHLIGHTS:
- SweRV Core EH2: The industry's first multi-threaded, commercial, embedded RISC-V core, SweRV Core EH2 supports the running of two simultaneous threads on top of its two-way superscalar architecture, enabling 6.3 Coremarks/Mhz simulated performance. The design includes double fetch buffers, instruction buffers, commit logic and other microarchitecture enhancements. This innovation may make it possible to reduce the number of CPUs in a device, thereby potentially saving programming time and cost associated with it, as well adding further flexibility to the data-centric architecture. Like SweRV Core EH1 (formerly referred to as SweRV Core 1.1) introduced early this year, EH2 is a 32-bit, 9 stage pipeline core and is ideal for use in embedded devices designed for data-intensive artificial intelligence (AI) and Internet-of-Things (IoT) applications.
- SweRV Core EL2: This ultra-small 3.6 Coremarks/Mhz simulated performance core, offers a 4-stage pipeline and is designed to replace sequential logic and state machines in controller system-on-chips, thereby programming time.
- Western Digital is also making it even easier for the ecosystem to implement RISC-V technologies into devices, with the availability of hardware implementation packages and technical support for the SweRV Core EH1 through GmbH (see separate announcement here).
- CHIPS ALLIANCE Broadens Support of Western Digital RISC-V Innovations: Western Digital's OmniXtend™ memory-centric system architecture is now managed by CHIPS ALLIANCE project, which is hosted by the Linux Foundation. OmniXtend is an open approach to providing cache coherent memory over an Ethernet fabric. It provides open standard interfaces for access and data sharing across processors, machine learning accelerators, GPUs, FPGAs and other components. Western Digital has contributed a hardware reference design that can be used to implement and test OmniXtend solutions. CHIPS ALLIANCE support enables the ecosystems to contribute, collaborate, develop, implement and OmniXtend. CHIPS ALLIANCE began managing Western Digital's SweRV Core portfolio earlier this year.